Removing Anti Dependences by Repairing

1 I n t r o d u c t i o n Computer designers and computer architects have been striving to improve uniprocessor performance since the invention of computers. The next step in this quest for higher performance is the exploitation of significant amounts of instruction-level parallelism. Therefore, superscalar and VLIW (very large instruction word) machines have been designed, which can execute several instructions in parallel. In order to use these resources the instructions are reordered by the hardware [Tho64, Tom67, PHS85, Soh90] or by compiler techniques like basic block instruction scheduling [LDSM80, HG83, GM86, EK92], trace scheduling [Fis81, El185] and software pipelining [RG81, Lam88, Ran94]. To ensure correctness, the order between dependent instructions must be maintained, which restricts reordering and parallelism. Dependences exist between writes and reads (data flow dependences), reads and writes (anti dependences) and between writes (output dependences) to the same register or memory location. In this paper, we will discuss only dependences through registers. We will also concentrate on anti dependences. Although the techniques discussed here can be used to eliminate output dependences, (partial) dead code elimination [KRS94, BC94] is more appropriate for this purpose. Another problem for exploiting significant amounts of instruction-level parallelism is the limited amount of registers (e.g., _< 32 integer registers on all